Characterization Lead

At Kandou , we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption. Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient . Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale. As Characterization Lead, you will own performance characterization of Zinal retimer silicon and the Randa Active Electrical Cable (AEC) channel. This is a Principal / Senior Staff individual contributor role with hands-on technical leadership. Your measurements will establish datasheet limits, channel classes and guard-bands for validation, manufacturing and customer specifications. Based primarily in Lausanne, you will work with silicon, signal integrity and validation teams, including channel characterization partners in Taiwan. Responsabilities · Lead silicon and channel characterization from measurement planning and bench setup through analysis, limit derivation and documented hand-off to validation. · Characterize TX/RX SerDes performance across process, voltage and temperature: swing, jitter, sensitivity, equalization, adaptation, CDR lock, BER bathtubs and shmoos. · Own channel measurements to at least 50 GHz, including de-embedding, insertion/return loss, mixed-mode S-parameters and common-mode and mode-conversion behavior. · Establish reference-paddle baselines and channel classes by gauge, reach and frequency; correlate HTDR-derived metrics with calibrated VNA measurements. · Derive datasheet limits and guard-bands from measured distributions, accounting for uncertainty, sample coverage and aging; maintain traceable datasets and limit revisions. · Assess carrier-loading and forwarded-clock tradeoffs using measured channel data and simulation, and translate the findings into supported configurations and characterization limits. · Characterize power, energy per bit and thermal behavior across operating modes and corners; investigate equalizer noise amplification and channel/thermal interactions. · Coordinate shared laboratory equipment and characterization milestones with validation teams; lead technical reviews and deliver limits in time for downstream qualification and screening. Essential Experience · 10 to 14 years of experience in SerDes/silicon characterization and/or high-speed channel and signal integrity characterization following degree completion. · Direct ownership of a characterization program whose results became datasheet limits or qualification thresholds for a shipping product. · Strong VNA measurement experience to 50 GHz or beyond, including de-embedding, mixed-mode S-parameters (Sdd/Scc/Scd/Sdc) and insertion/return-loss mask interpretation. · Hands-on TX/RX SerDes characterization, jitter decomposition, BER bathtubs, PVT shmoos and equalization/adaptation analysis. · Demonstrated common-mode and mode-conversion measurement depth, with the ability to distinguish channel behavior from fixture and calibration artifacts. · Statistical characterization and guard-band derivation across corners, with clear treatment of measurement uncertainty, sample size and aging. · Experience with VNAs, oscilloscopes of at least 50 GHz bandwidth, BERTs, jitter instrumentation, thermal forcing and ATE characterization load boards. · BS in Electrical Engineering or equivalent, with the technical communication and coordination skills to hand off defensible limits to validation and manufacturing teams. Essential Experience · Characterization leadership for shipping 100G/lane or 200G/lane retimers, PHYs, AECs or AOCs. · Deep mixed-mode characterization where common-mode behavior affects information transport and link