AI Modelling and Simulation Engineer

The Opportunity Lumai is moving from breakthrough optical-compute research to production AI systems. We need an engineer to build the performance and power modelling capability that guides architecture and compiler decisions before silicon exists, helping us turn a working system into a competitive product. The Role You will own the performance and power modelling framework that predicts how Lumai’s photonic AI hardware will perform against real inference workloads. Your models will give architecture and compiler teams a shared source of truth for latency, throughput and power across hardware configurations. The hard part is balancing speed, fidelity and usability: you will model concurrency, event-driven behaviour and compute-block latency at enough detail to support decisions, while keeping simulations fast enough to compare configurations in minutes. You will characterise operator-level workloads against hardware, RTL or emulation results so the model stays grounded in evidence. By month six, you will have established a reliable modelling flow for priority workloads and device configurations, demonstrated a clear path for closing gaps between model and hardware, and made the simulator a tool that architecture and compiler teams use to make decisions. You will report to the Head of Architecture or VP Engineering and may build and lead a small team around this capability. What You'll Do Design, build and maintain a Python-based framework that models hardware and software latency, hardware concurrency and event-driven relationships. Model compute engines, interconnect and synchronisation fabric, memory and bridge interfaces, and accelerator blocks across device configurations. Characterise convolution, depthwise convolution, pooling, attention and other operator workloads against hardware, RTL or emulation results. Build compiler-agnostic interfaces that ingest compiled models and MLIR from multiple internal compiler flows. Analyse simulation traces with architecture and compiler teams to improve layer-to-hardware mappings and resolve performance discrepancies. Run industry benchmarks and representative models, including UL Procyon, Geekbench AI, Stable Diffusion and contemporary LLMs, to produce decision-ready KPIs. Develop block-level power models and validate worst-case power scenarios with micro-architecture, verification and physical-design teams. Own the CI/CD pipelines and simulation flows that keep results reliable and reproducible as usage scales. Translate modelling findings into architecture and compiler decisions, while setting technical direction and developing engineers or interns as the team grows. What We're Looking For Must-have Proven experience building or substantially extending a hardware/software performance-modelling or simulation framework for AI/ML accelerators, ideally in Python. Strong understanding of hardware concurrency, event-driven modelling, and AI inference accelerator micro-architecture, including compute, memory hierarchy, interconnect and dataflow. Hands-on experience characterising AI operators and correlating model predictions with real hardware or hardware-accurate reference data. Familiarity with compiler internals and intermediate representations such as MLIR, including tooling that consumes compiler output to drive simulation. Strong software-engineering and technical-leadership practice, including framework design, CI/CD ownership and direction or review of work by junior engineers or interns. Strong preference for Direct experience with NPU, GPU or other edge or client AI inference accelerator architectures. Experience working across multiple compiler toolchains and reconciling architecture-level and production compiler behaviour. Exposure to power modelling, RTL, emulation, FPGA prototyping, photonic compute or another non-traditional compute architecture. About Lumai Lumai is the optical compute company building the next genera