Senior Digital IC Design Engineer
Quantum Motion Technologies - Personio London, UKEst. Est. GBP 70,000–95,000 / yearSenior
Estimated range based on role, country and industry — not published by the company.
Key requirements
- Python
About The Role and Team Quantum Motion is a fast-growing quantum computing scale-up based in London founded by internationally renowned researchers from UCL and Oxford University with over 40 years’ experience in developing qubits and quantum computing architectures. Bringing together state-of-the-art cryogenic facilities and an outstanding interdisciplinary team, we are developing quantum processors based on industrial-grade silicon chips, with the potential to radically transform computing power in areas such as materials modelling, medicine, artificial intelligence and more.
Our Team Since 2021 our team has been listed every year in the “Top 100 Startups worth watching” in the EE Times in 2021 and 2022, and our technology breakthroughs have been featured in The Telegraph , BBC and the New Statesman . Our founders are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We’re backed by a team of top-tier investors, and we have recently closed our Series C funding of $160 million.
We bring together the brightest quantum engineers, integrated circuit (IC) engineers, quantum computing theoreticians and software engineers to create a unique, world-leading team, working together closely to maximise our combined expertise. Our collaborative and interdisciplinary culture is an ideal fit for anyone who thrives in a cutting-edge research and development environment focused on tackling big challenges and contributing to the development of scalable quantum computers based on silicon technology. This is a rare and exciting opportunity to be an employee at a scale-up shaping the future of quantum computing. There are vast opportunities for professional growth and to make an impact within the company. Our team of 100+ is based across London, Oxford, San Sebastián and Sydney, with our primary hub in Islington (London).
Functions of the Role This senior position operates at the critical intersection of sub-Kelvin sub-system electronics and quantum processor architectures, directly addressing the interconnect bottleneck in scalable quantum computing systems. The role spans the full digital IC design cycle—including initial microarchitecture specification, RTL development, Verilog-AMS co-simulation, physical implementation (PnR/CTS), low-power synthesis, static timing analysis (STA), and full tape-out signoff. The ultimate objective is the realization of ultra-low-power, high-density cryogenic control ICs tailored for fault-tolerant quantum computing scale-out.
Position Title: Senior Digital Designer (Front-End & Back-End)
Domain Focus: Ultra-Low-Power Cryogenic CMOS (Cryo-CMOS) Digital Control Sub-circuits
Design Scope: Full Lifecycle (RTL Development, AMS Co-Simulation, Physical Implementation, Low-Power Synthesis, and Tape-Out Signoff)
Core Chip Architecture Target: Cryogenic digital logic blocks operating at sub-Kelvin regimes (
Experience - Essentials Education: Master's degree or Ph.D. in Electrical Engineering, Microelectronics, Computer Engineering, or related technical discipline.
Chip Design Experience: 5+ years of hands-on digital and mixed-signal IC design, demonstrating successful completion of at least 2 tape-outs on advanced semiconductor nodes
Hardware Coding: Proficiency in Verilog and SystemVerilog for synthesizable RTL development and Verilog-AMS/SystemVerilog-Real-Math for mixed-signal co-simulation and testbench environments.
Design Tools: Proven proficiency with industry-standard EDA toolchains (e.g., Cadence Virtuoso/Innovus/Xcelium, Synopsys Design Compiler) for mixed-signal simulation, synthesis, and verification.
Physical Layout: Demonstrated capability in transforming RTL into GDSII/OASIS physical layouts, floorplanning, power grid synt
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