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Photonics Layout Lead

Salience Labs Oxford, United KingdomEst. Est. GBP 75,000–105,000 / yearSenior

Estimated range based on role, country and industry — not published by the company.

Key requirements

  • Python
About us Salience Labs is building the optical infrastructure that will power the next generation of AI. Our photonic switching technology delivers the high-speed, ultra-low latency networking fabrics AI datacenters need and can’t get anywhere else. We’re a multi-disciplinary team of physicists, engineers, and machine learning specialists on a mission to remove the bottlenecks holding AI infrastructure back. Job Overview We are looking for a Photonics Layout Lead to join our Photonics team and lead our Layout team, taking technical and people leadership of the physical design, verification and development of advanced integrated photonic devices. You will work closely with engineers across photonic design, layout and testing, setting the direction for how device and circuit requirements are translated into robust, fabrication-ready layouts. The role combines hands-on physical layout, design verification, programming and ownership of our internal design workflows, along with leading, developing and managing the layout engineers on your team and raising the standard of layout work across the company. This is a hands-on leadership role for someone who enjoys working at the intersection of integrated photonics, semiconductor design and software. You should be comfortable leading the resolution of complex layout challenges, interpreting and challenging design requirements, and using programming to improve the speed, quality and repeatability of engineering work, while building a team that can do the same. We are particularly interested in people who have led or significantly shaped integrated photonics or semiconductor IC layout work, and who have experience leading engineers, whether in industry, research or a strong academic environment. What you’ll be doing Lead the Layout team, setting priorities, allocating work and ensuring the team delivers high-quality, on-time results Line manage layout engineers, including coaching, performance reviews, career development and objective setting Support hiring and onboarding of new layout engineers as the team grows Lead the development of physical layouts for integrated photonic components, structures and large-scale photonic designs Translate photonic device and circuit requirements into fabrication-ready layouts, and help shape those requirements with the photonic design team Own design verification, including DRC and LVS, and drive designs through the full layout and verification process to tape-out Define, develop and improve software-based workflows for photonic layout and design automation Use Python and relevant semiconductor or photonic design tools to create, manipulate and verify layouts, and set best practice for the team to do the same Own and evolve our internal component and design libraries Define and support the development of appropriate test and characterisation structures Lead layout reviews for design integrity, fabrication constraints and potential sources of failure Act as a technical point of contact for foundry and fabrication partners on design rules, process constraints and verification issues Plan and prioritise layout work across projects, balancing schedule, quality, risk and team capacity Collaborate closely with photonic design, testing and wider engineering teams, and represent the Layout team in planning and design discussions Drive improvements in layout methodology, tooling and verification processes Make photonic design workflows increasingly repeatable, reliable and efficient You will own the Layout team’s technical direction and delivery, from individual components through to complex, full-chip integrated photonic designs and their verification. What we’re looking for A Bachelor’s degree or equivalent in Physics, Photonics, Electrical Engineering, Optical Engineering, or another closely related technical discipline Typically 6+ years of relevant experience in integrated photonics, photonic IC layout,

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